1. Field of the Invention
The present invention pertains to the field of integrated circuits. More particularly, this invention relates to an amplifier circuit that employs dynamic output stage biasing for enhanced output current drive capability.
2. Art Background
FIG. 1 illustrates a typical prior operational amplifier circuit having a gain stage 10 and an output stage 12. The output stage 12 operates in the CLASS AB mode. The output stage 12 comprises a set of transistors Q.sub.1 through Q4 and a pair of electrical current sources S1 and S2. The electrical current source S1 supplies an electrical current I.sub.1 to the base of the transistor Q.sub.3. Similarly, the electrical current source S2 supplies an electrical current I.sub.2 to the base of the transistor Q.sub.4.
The output stage 12 sinks an electrical load current I.sub.OUT into an output node 14 in the direction shown. As the magnitude of the electrical current I.sub.OUT increases due to external loading factors, the base of the transistor Q.sub.4 requires increasing amounts of electrical current from the current source S2 to meet the increased demand.
In addition, the amount of electrical current flowing through the emitter of the transistor Q.sub.1 decreases as the base of the transistor Q.sub.4 draws increasing amounts of electrical current. Such a decrease in the amount of electrical current flowing through the emitter of the transistor Q.sub.1 is a direct consequence of the increased demand for I2 electrical current to the base of the transistor Q.sub.4 to satisfy the changing demands of external load at the output node 14.
Unfortunately, the amount of electrical current available to the base of the transistor Q.sub.4 reaches an upper limit as the decreasing amount of electrical current flowing through the emitter of the transistor Q.sub.1 reaches zero. Moreover, the amount of electrical output current I.sub.OUT sinking into the output node 14 cannot be increased once the electrical current flow through the emitter of the transistor Q.sub.1 reaches zero. The upper limit on maximum output current sinking at the output node 14 is given by EQU I.sub.OUT (max)=(B.sub.p+1)*I.sub.2
where B.sub.p is the electrical current gain of the transistor Q.sub.4. The electrical current gain of the transistor Q.sub.4 is given by EQU B.sub.P =I.sub.C /I.sub.B
where I.sub.C is the collector current through the transistor Q.sub.4 and where I.sub.B is the base current of the transistor Q.sub.4.
Moreover, temperature variations of the output stage 12 along with process control variations during device manufacture typically cause a wide variation in the actual values of B.sub.P among differing devices. As a consequence, the amount of electrical current I.sub.OUT that the output stage 12 can sink at the output node 14 is limited by low values of B.sub.P for the transistor Q.sub.4.
One prior approach to overcoming such a limitation on the electrical current I.sub.OUT is to increase the amount of electrical current I.sub.2 supplied from the current source S2. Unfortunately, such an augmented current source increases the amount of DC electrical power consumption of the output stage 12, and thereby increases the power consumption of any system that employs such an operational amplifier.